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16-Bit, 1.33 MSPS PulSAR ADC in MSOP/QFN AD7983
FEATURES
16-bit resolution with no missing codes Throughput: 1.33 MSPS Low power dissipation: 10.5 mW typical @ 1.33 MSPS INL: 0.6 LSB typical, 1.0 LSB maximum SINAD: 91.6 dB @ 10 kHz THD: -115 dB @ 10 kHz Pseudo differential analog input range 0 V to VREF with VREF between 2.9 V to 5.5 V Any input range and easy to drive with the ADA4841 No pipeline delay Single-supply 2.5 V operation with 1.8 V/2.5 V/3 V/5 V logic interface Serial interface SPI-/QSPITM-/MICROWIRETM-/DSP-compatible Daisy-chain multiple ADCs and busy indicator 10-lead MSOP (MSOP-8 size) and 10-lead 3 mm x 3 mm QFN 1 (LFCSP), SOT-23 size Wide operating temperature range: -40C to +85C
APPLICATION DIAGRAM
2.9V TO 5V 2.5V
0 TO VREF IN+ IN-
REF VDD VIO SDI
1.8V TO 5V 3- OR 4-WIRE INTERFACE (SPI, DAISY CHAIN, CS)
06974-001
AD7983
GND
SCK SDO CNV
Figure 1.
GENERAL DESCRIPTION
The AD7983 is a 16-bit, successive approximation, analog-todigital converter (ADC) that operates from a single power supply, VDD. It contains a low power, high speed, 16-bit sampling ADC and a versatile serial interface port. On the CNV rising edge, it samples an analog input IN+ between 0 V to REF with respect to a ground sense IN-. The reference voltage, REF, is applied externally and can be set independent of the supply voltage, VDD. Its power scales linearly with throughput. The SPI-compatible serial interface also features the ability, using the SDI input, to daisy-chain several ADCs on a single, 3-wire bus and provides an optional busy indicator. It is compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic, using the separate supply VIO. The AD7983 is housed in a 10-lead MSOP or a 10-lead QFN1 (LFCSP) with operation specified from -40C to +85C.
APPLICATIONS
Battery-powered equipment Communications ATE Data acquisitions Medical instruments
1
QFN package in development. Contact sales for samples and availability.
Table 1. MSOP, QFN (LFCSP) 14-/16-/18-Bit PulSAR(R) ADC
Type 14-Bit 16-Bit 100 kSPS AD7940 AD7680 AD7683 AD7684 250 kSPS AD79422 AD76852 AD76872 AD7694 AD7691 2 400 kSPS to 500 kSPS AD79462 AD76862 AD76882 AD76932 AD76902 1000 kSPS AD79802 AD79832 AD79822 AD79842 ADC Driver ADA4941 ADA4841 ADA4941 ADA4841
1
18-Bit
1 2
QFN package in development. Contact sales for samples and availability. Pin-for-pin compatible.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2007 Analog Devices, Inc. All rights reserved.
AD7983 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Application Diagram........................................................................ 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Specifications....................................................................... 5 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configurations and Function Descriptions ........................... 7 Typical Performance Characteristics ............................................. 8 Terminology .................................................................................... 11 Theory of Operation ...................................................................... 12 Circuit Information.................................................................... 12 Converter Operation.................................................................. 12 Typical Connection Diagram ................................................... 13 Analog Inputs.............................................................................. 14 Driver Amplifier Choice ........................................................... 14 Voltage Reference Input ............................................................ 15 Power Supply............................................................................... 15 Digital Interface.......................................................................... 16 CS MODE, 3-Wire Without Busy Indicator........................... 17 CS Mode, 3-Wire with Busy Indicator .................................... 18 CS Mode, 4-Wire Without Busy Indicator ............................. 19 CS Mode, 4-Wire with Busy Indicator .................................... 20 Chain Mode Without Busy Indicator ...................................... 21 Chain Mode with Busy Indicator............................................. 22 Application Hints ........................................................................... 23 Layout .......................................................................................... 23 Evaluating the Performance of the AD7983............................... 23 Outline Dimensions ....................................................................... 24 Ordering Guide .......................................................................... 24
REVISION HISTORY
11/07--Revision 0: Initial Version
Rev. 0 | Page 2 of 24
AD7983 SPECIFICATIONS
VDD = 2.5 V, VIO = 2.3 V to 5.5 V, REF = 5 V, TA = -40C to +85C, unless otherwise noted. Table 2.
Parameter RESOLUTION ANALOG INPUT Voltage Range Absolute Input Voltage Analog Input CMRR Leakage Current @ 25C Input Impedance ACCURACY No Missing Codes Differential Linearity Error Integral Linearity Error Transition Noise Gain Error, TMIN to TMAX 3 Gain Error Temperature Drift Zero Error, TMIN to TMAX3 Zero Temperature Drift Power Supply Sensitivity THROUGHPUT Conversion Rate Transient Response AC ACCURACY Dynamic Range Signal-to-Noise Ratio, SNR Spurious-Free Dynamic Range, SFDR Total Harmonic Distortion, THD Signal-to-(Noise + Distortion), SINAD
1 2 3
Conditions
Min 16 0 -0.1 -0.1
Typ
Max
Unit Bits V V V dB 1 nA
IN+ - IN- IN+ IN- fIN = 100 kHz Acquisition phase
VREF VREF + 0.1 +0.1
60 1 See the Analog Inputs section 16 -0.9 -1.0
-0.9 VDD = 2.5 V 5% 0 Full-scale step
0.4 0.6 0.52 2 0.41 0.44 0.54 0.1
+0.9 +1.0
+0.9
Bits LSB 2 LSB2 LSB2 LSB2 ppm/C mV ppm/C LSB2 MSPS ns dB1 dB1 dB1 dB1 dB1
1.33 290 93 92 114 -115 91.6
fIN = 1 kHz fIN = 10 kHz fIN = 10 kHz fIN = 10 kHz
90.5
All specifications in dB are referred to a full-scale input FSR. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified. LSB means least significant bit. With the 5 V input range, 1 LSB is 76.3 V. See the Terminology section. These specifications include full temperature range variation, but not the error contribution from the external reference.
Rev. 0 | Page 3 of 24
AD7983
VDD = 2.5 V, VIO = 2.3 V to 5.5 V, REF = 5 V, TA = -40C to +85C, unless otherwise noted. Table 3.
Parameter REFERENCE Voltage Range Load Current SAMPLING DYNAMICS -3 dB Input Bandwidth Aperture Delay DIGITAL INPUTS Logic Levels VIL VIH VIL VIH IIL IIH DIGITAL OUTPUTS Data Format Pipeline Delay VOL VOH POWER SUPPLIES VDD VIO VIO Range Standby Current 1, 2 Power Dissipation Energy per Conversion TEMPERATURE RANGE 3 Specified Performance
1 2
Conditions
Min 2.9
Typ
Max 5.1
Unit V A MHz ns
1.33 MSPS
500 10 2.0
VIO > 3V VIO > 3V VIO 3V VIO 3V
-0.3 0.7 x VIO -0.3 0.9 x VIO -1 -1
0.3 x VIO VIO + 0.3 0.1 x VIO VIO + 0.3 +1 +1
V V V V A A
ISINK = 500 A ISOURCE = -500 A
Serial 16 bits straight binary Conversion results available immediately after completed conversion 0.4 VIO - 0.3 2.375 2.3 1.8 2.5 2.625 5.5 5.5 12
V V V V V nA mW nJ/sample C
Specified performance VDD and VIO = 2.5 V 1.33 MSPS throughput
0.35 10.5 7.9 -40
TMIN to TMAX
+85
With all digital inputs forced to VIO or GND as required. During the acquisition phase. 3 Contact sales for extended temperature range.
Rev. 0 | Page 4 of 24
AD7983 TIMING SPECIFICATIONS
TA = -40C to +85C, VDD = 2.37 V to 2.63 V, VIO = 3.3 V to 5.5 V, unless otherwise noted. See Figure 2 and Figure 3 for load conditions. Table 4.
Parameter Conversion Time: CNV Rising Edge to Data Available Acquisition Time Time Between Conversions CNV Pulse Width (CS Mode) SCK Period (CS Mode) VIO Above 4.5 V VIO Above 3 V VIO Above 2.7 V VIO Above 2.3 V SCK Period (Chain Mode) VIO Above 4.5 V VIO Above 3 V VIO Above 2.7 V VIO Above 2.3 V SCK Low Time SCK High Time SCK Falling Edge to Data Remains Valid SCK Falling Edge to Data Valid Delay VIO Above 4.5 V VIO Above 3 V VIO Above 2.7 V VIO Above 2.3 V CNV or SDI Low to SDO D15 MSB Valid (CS Mode) VIO Above 3 V VIO Above 2.3 V CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) SDI Valid Setup Time from CNV Rising Edge SDI Valid Hold Time from CNV Rising Edge (CS Mode) SDI Valid Hold Time from CNV Rising Edge (Chain Mode) SCK Valid Setup Time from CNV Rising Edge (Chain Mode) SCK Valid Hold Time from CNV Rising Edge (Chain Mode) SDI Valid Setup Time from SCK Falling Edge (Chain Mode) SDI Valid Hold Time from SCK Falling Edge (Chain Mode) SDI High to SDO High (Chain Mode with Busy Indicator) Symbol tCONV tACQ tCYC tCNVH tSCK Min 300 250 750 10 10.5 12 13 15 tSCK 11.5 13 14 16 4.5 4.5 3 9.5 11 12 14 tEN 10 15 20 5 2 0 5 5 2 3 15 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Typ Max 500 Unit ns ns ns ns ns ns ns ns
tSCKL tSCKH tHSDO tDSDO
tDIS tSSDICNV tHSDICNV tHSDICNV tSSCKCNV tHSCKCNV tSSDISCK tHSDISCK tDSDOSDI
500A
IOL
X% VIO1
Y% VIO1
tDELAY
TO SDO CL 20pF
06974-002
tDELAY
VIH2 VIL2 VIH2 VIL2
06974-003
1.4V
500A
IOH
1FOR VIO 3.0V, X = 90 AND Y = 10; FOR VIO > 3.0V X = 70, AND Y = 30. 2MINIMUM V AND MAXIMUM V USED. SEE DIGITAL INPUTS IH IL
SPECIFICATIONS IN TABLE 3.
Figure 2. Load Circuit for Digital Interface Timing
Figure 3. Voltage Levels for Timing
Rev. 0 | Page 5 of 24
AD7983 ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Analog Inputs IN+, 1 IN-1 to GND Supply Voltage REF, VIO to GND VDD to GND VDD to VIO Digital Inputs to GND Digital Outputs to GND Storage Temperature Range Junction Temperature JA Thermal Impedance 10-Lead MSOP 10-Lead QFN 2 (LFCSP) JC Thermal Impedance 10-Lead MSOP 10-Lead QFN2 (LFCSP) Lead Temperature Vapor Phase (60 sec) Infrared (15 sec)
1 2
Rating -0.3 V to VREF + 0.3 V or 130 mA -0.3 V to +6 V -0.3 V to +3 V -0.3 V to +6 V -0.3 V to VIO + 0.3 V -0.3 V to VIO + 0.3 V -65C to +150C 150C 200C/W 48.7C/W 44C/W 2.96C/W 215C 220C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
See the Analog Inputs section. QFN package in development. Contact sales for samples and availability.
Rev. 0 | Page 6 of 24
AD7983 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
REF 1 VDD 2 IN+ 3 IN- 4 GND 5
10 VIO
REF 1 VDD 2 IN+ 3
06974-004
10 VIO
TOP VIEW (Not to Scale)
AD7983
9 8 7 6
SDI SCK SDO CNV
AD7983
TOP VIEW (Not to Scale)
9 SDI 8 SCK 7 SDO 6 CNV
06974-005
IN- 4 GND 5
Figure 4. 10-Lead MSOP Pin Configuration
1
Figure 5. 10-Lead QFN 1 (LFCSP) Pin Configuration
QFN package in development. Contact sales for samples and availability.
Table 6. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 Mnemonic REF VDD IN+ IN- GND CNV Type 1 AI P AI AI P DI Description Reference Input Voltage. The REF range is from 2.9 V to 5.1 V. It is referred to the GND pin. This pin should be decoupled closely to the pin with a 10 F capacitor. Power Supply. Analog Input. It is referred to IN-. The voltage range, for example, the difference between IN+ and IN-, is 0 V to VREF. Analog Input Ground Sense. To be connected to the analog ground plane or to a remote sense ground. Power Supply Ground. Convert Input. This input has multiple functions. On its risng edge, it initiates the conversions and selects the interface mode of the part: chain or CS mode. In CS mode, it enables the SDO pin when low. In chain mode, the data should be read when CNV is high. Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock. Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows: Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI is output on SDO with a delay of 16 SCK cycles. CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable the serial output signals when low; if SDI or CNV is low when the conversion is complete, the busy indicator feature is enabled. Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V).
7 8 9
SDO SCK SDI
DO DI DI
10
1
VIO
P
AI = analog input, DI = digital input, DO = digital output, and P = power.
Rev. 0 | Page 7 of 24
AD7983 TYPICAL PERFORMANCE CHARACTERISTICS
VDD = 2.5 V, REF = 5 V, VIO = 3.3 V, unless otherwise noted.
1.25 1.00 0.75 0.50 0.50 0.25 0 -0.25 -0.50 -0.50 -0.75
06974-026
POSITIVE INL: 0.30LSB NEGATIVE INL: -0.37LSB
1.00 0.75 POSITIVE DNL: 0.14LSB NEGATIVE DNL: -0.14LSB
DNL (LSB)
0.25 0 -0.25
INL (LSB)
-1.00 -1.25 0 16384 32768 CODE 49152
65536
-1.00
0
16384
32768 CODE
49152
65536
Figure 6. Integral Nonlinearity vs. Code
120k 80k 70k 60k 80k 50k
Figure 9. Differential Nonlinearity vs. Code
100k
96765
67532 61565
COUNTS
COUNTS
60k
40k 30k 20k
40k 17590
06974-041
20k 0 0 0 0 58
16604
0
55
0
0
0
0
0
0
0
0
0
829
1146 0
0
0
0
0
7FB6 7FB7 7FB8 7FB9 7FBA 7FBB 7FBC 7FBD 7FBE 7FBF 7FC0 7FC1 7FC2
7FF7 7FF8 7FF9 7FFA 7FFB 7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003
CODE IN HEX
CODE IN HEX
Figure 7. Histogram of a DC Input at the Code Center
0 -20
Figure 10. Histogram of a DC Input at the Code Transition
95 94 93 92
AMPLITUDE (dB of Full Scale)
-40 -60 -80 -100 -120 -140
SNR = 91.6dB THD = -114.9dB SFDR = 113.8dB SINAD = 91.6dB
fS = 1.33MSPS fIN = 10kHz
SNR (dB)
91 90 89 88 87
06974-028
86 85 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0
-180
0
100
200
300
400
500
600
FREQUENCY (kHz)
INPUT LEVEL (dB of Full Scale)
Figure 8. FFT Plot
Figure 11. SNR vs. Input Level
Rev. 0 | Page 8 of 24
06974-032
-160
06974-042
10k
06974-029
-0.75
AD7983
-110 95
-112
93
THD (dB)
SNR (dB)
-114
91
-116
89
-118
06974-038
87
06974-035
-120 -55
-35
-15
5
25
45
65
85
105
125
85 -55
-35
-15
5
25
45
65
85
105
125
TEMPERATURE (C)
TEMPERATURE (C)
Figure 12. THD vs. Temperature
-105 130 100
Figure 15. SNR vs. Temperature
16
-110
125 95 15 ENOB SNR
90
SINAD
14
-120 SFDR -125
115
85 110
13
3.0
3.5
4.0
4.5
5.0
3.0
3.5
4.0
4.5
5.0
REFERENCE VOLTAGE (V)
REFERENCE VOLTAGE (V)
Figure 13. THD, SFDR vs. Reference Voltage
100 95 90
Figure 16. SNR, SINAD, and ENOB vs. Reference Voltage
-70 -75 -80 -85
SINAD (dB)
THD (dB)
85 80 75 70 65
-90 -95 -100 -105 -110 -115 -120 1 10 FREQUENCY (kHz) 100
06974-037
1
10 FREQUENCY (kHz)
100
1000
06974-034
1000
Figure 14. SINAD vs. Frequency
Figure 17. THD vs. Frequency
Rev. 0 | Page 9 of 24
06974-031
06974-033
-130 2.5
105 5.5
80 2.5
12 5.5
ENOB (Bits)
SFDR (dB)
THD (dB)
-115
THD
120
SNR, SINAD (dB)
AD7983
2.5 IVDD
1.5 1.4 1.3
OPERATING CURRENTS (mA)
2.0
STANDBY CURRENTS (mA)
1.2 1.1 1.0 0.9 0.8 0.7 IVDD + IVIO
1.5
1.0 IREF 0.5
06974-036
0.6 0.5 -55 -35 -15 5 25 45 65 85 105
0 2.375
2.425
2.475
2.525
2.575
2.625
125
VDD VOLTAGE (V)
TEMPERATURE (C)
Figure 18. Operating Currents vs. Supply
2.5 IVDD
Figure 20. Standby Currents vs. Temperature
OPERATING CURRENTS (mA)
2.0
1.5
1.0
0.5
IREF
06974-039
IVIO 0 -55
-35
-15
5
25
45
65
85
105
125
TEMPERATURE (C)
Figure 19. Operating Currents vs. Temperature
Rev. 0 | Page 10 of 24
06974-040
IVIO
AD7983 TERMINOLOGY
Integral Nonlinearity Error (INL) INL refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as a level 11/2 LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (see Figure 22). Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Offset Error The first transition should occur at a level 1/2 LSB above analog ground (38.1 V for the 0 V to 5 V range). The offset error is the deviation of the actual transition from that point. Gain Error The last transition (from 111 ... 10 to 111 ... 11) should occur for an analog voltage 11/2 LSB below the nominal full scale (4.999886 V for the 0 V to 5 V range). The gain error is the deviation of the actual level of the last transition from the ideal level after the offset is adjusted out. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD as follows: ENOB = (SINADdB - 1.76)/6.02 and is expressed in bits. Noise-Free Code Resolution Noise-free code resolution is the number of bits beyond which it is impossible to distinctly resolve individual codes. It is calculated as Noise-Free Code Resolution = log2(2N/Peak-to-Peak Noise) and is expressed in bits. Effective Resolution Effective resolution is calculated as Effective Resolution = log2(2N/RMS Input Noise) and is expressed in bits. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in dB. Dynamic Range Dynamic range is the ratio of the rms value of the full scale to the total rms noise measured with the inputs shorted together. The value for dynamic range is expressed in dB. It is measured with a signal at -60 dBFS to include all noise sources and DNL artifacts. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in dB. Signal-to-(Noise + Distortion) Ratio (SINAD) SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in dB. Aperture Delay Aperture delay is the measurement of the acquisition performance. It is the time between the rising edge of the CNV input and when the input signal is held for a conversion. Transient Response Transient response is the time required for the ADC to accurately acquire its input after a full-scale step function is applied.
Rev. 0 | Page 11 of 24
AD7983 THEORY OF OPERATION
IN+ MSB LSB 32,768C REF COMP GND 32,768C 16,384C MSB 4C 2C C C LSB SW- CNV 16,384C 4C 2C C C CONTROL LOGIC OUTPUT CODE SWITCHES CONTROL SW+ BUSY
IN-
Figure 21. ADC Simplified Schematic
CIRCUIT INFORMATION
The AD7983 is a fast, low power, single-supply, precise 16-bit ADC that uses a successive approximation architecture. The AD7983 is capable of converting 1,000,000 samples per second (1 MSPS) and powers down between conversions. When operating at 10 kSPS, for example, it consumes 70 W typically, making it ideal for battery-powered applications. The AD7983 provides the user with an on-chip track-and-hold and does not exhibit any pipeline delay or latency, making it ideal for multiple multiplexed channel applications. The AD7983 can be interfaced to any 1.8 V to 5 V digital logic family. It is available in a 10-lead MSOP or a tiny 10-lead QFN 1 (LFCSP) that allows space savings and flexible configurations. It is pin-for-pin compatible with the 18-bit AD7982.
CONVERTER OPERATION
The AD7983 is a successive approximation ADC based on a charge redistribution DAC. Figure 21 shows the simplified schematic of the ADC. The capacitive DAC consists of two identical arrays of 16 binary weighted capacitors, which are connected to the two comparator inputs.
During the acquisition phase, terminals of the array tied to the input of the comparator are connected to GND via SW+ and SW-. All independent switches are connected to the analog inputs. Therefore, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the IN+ and IN- inputs. When the acquisition phase is complete and the CNV input goes high, a conversion phase is initiated. When the conversion phase begins, SW+ and SW- are opened first. The two capacitor arrays are then disconnected from the inputs and connected to the GND input. Therefore, the differential voltage between the inputs IN+ and IN- captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between GND and REF, the comparator input varies by binary weighted voltage steps (VREF/2, VREF/4 ... VREF/65,536). The control logic toggles these switches, starting with the MSB, to bring the comparator back into a balanced condition. After the completion of this process, the part returns to the acquisition phase and the control logic generates the ADC output code and a busy signal indicator. Because the AD7983 has an on-board conversion clock, the serial clock, SCK, is not required for the conversion process.
1
QFN package in development. Contact sales for samples and availability.
Rev. 0 | Page 12 of 24
06974-006
AD7983
Transfer Functions
The ideal transfer characteristic for the AD7983 is shown in Figure 22 and Table 7.
111 ... 111
Table 7. Output Codes and Ideal Input Voltages
Description FSR - 1 LSB Midscale + 1 LSB Midscale Midscale - 1 LSB -FSR + 1 LSB -FSR
1 2
ADC CODE (STRAIGHT BINARY)
111 ... 110 111 ... 101
VREF = 5 V 4.999924 V 2.500076 V 2.5 V 2.499924 V 76.3 V 0V
Analog Input Digital Output Code (Hex) FFFF1 8001 8000 7FFF 0001 00002
This is also the code for an overranged analog input (VIN+ - VIN- above VREF - VGND). This is also the code for an underranged analog input (VIN+ - VIN- below VGND).
TYPICAL CONNECTION DIAGRAM
000 ... 010 000 ... 001 000 ... 000 -FSR -FSR + 1LSB -FSR + 0.5LSB +FSR - 1 LSB +FSR - 1.5 LSB ANALOG INPUT
Figure 23 shows an example of the recommended connection diagram for the AD7983 when multiple supplies are available.
06974-007
Figure 22. ADC Ideal Transfer Function
V+
REF1 10F2 100nF
2.5V
V+ 20 0 TO VREF V- 4 IN- GND 2.7nF IN+ REF VDD VIO SDI SCK 100nF
1.8V TO 5V
AD7983
3- OR 4-WIRE INTERFACE SDO CNV
1SEE
4OPTIONAL 5SEE
FILTER. SEE THE ANALOG INPUTS SECTION. THE DIGITAL INTERFACE SECTION FOR THE MOST CONVENIENT INTERFACE MODE.
Figure 23. Typical Application Diagram with Multiple Supplies
Rev. 0 | Page 13 of 24
06974-008
2C REF IS USUALLY A 10F CERAMIC CAPACITOR 3SEE THE DRIVER AMPLIFIER CHOICE SECTION.
THE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION. (X5R).
AD7983
ANALOG INPUTS
Figure 24 shows an equivalent circuit of the input structure of the AD7983. The two diodes, D1 and D2, provide ESD protection for the analog inputs, IN+ and IN-. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 0.3 V, because this causes these diodes to become forwardbiased and start conducting current. These diodes can handle a forward-biased current of 130 mA maximum. For instance, these conditions could eventually occur when the supplies of the input buffer (U1) are different from VDD. In such a case (for example, an input buffer with a short circuit), the current limitation can be used to protect the part.
REF
DRIVER AMPLIFIER CHOICE
Although the AD7983 is easy to drive, the driver amplifier needs to meet the following requirements: * The noise generated by the driver amplifier needs to be kept as low as possible to preserve the SNR and transition noise performance of the AD7983. The noise coming from the driver is filtered by the AD7983 analog input circuit's 1-pole, low-pass filter made by RIN and CIN or by the external filter, if one is used. Because the typical noise of the AD7983 is 39.7 V rms, the SNR degradation due to the amplifier is
SNRLOSS
39.7 = 20 log 2 2 39.7 + f -3dB (Ne N ) 2

D1 IN+ OR IN- CPIN GND D2
RIN
CIN
Figure 24. Equivalent Analog Input Circuit
The analog input structure allows the sampling of the true differential signal between IN+ and IN-. By using these differential inputs, signals common to both inputs are rejected. During the acquisition phase, the impedance of the analog inputs (IN+ and IN-) can be modeled as a parallel combination of capacitor, CPIN, and the network formed by the series connection of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically 400 and is a lumped component made up of some serial resistors and the on resistance of the switches. CIN is typically 30 pF and is mainly the ADC sampling capacitor. During the conversion phase, where the switches are opened, the input impedance is limited to CPIN. RIN and CIN make a 1-pole, low-pass filter that reduces undesirable aliasing effects and limits the noise. When the source impedance of the driving circuit is low, the AD7983 can be driven directly. Large source impedances significantly affect the ac performance, especially THD. The dc performances are less sensitive to the input impedance. The maximum source impedance depends on the amount of THD that can be tolerated. The THD degrades as a function of the source impedance and the maximum input frequency.
where: f-3dB is the input bandwidth in MHz of the AD7983 (10 MHz) or the cutoff frequency of the input filter, if one is used. N is the noise gain of the amplifier (for example, 1 in buffer configuration). eN is the equivalent input noise voltage of the op amp, in nV/Hz. * * For ac applications, the driver should have a THD performance commensurate with the AD7983. For multichannel multiplexed applications, the driver amplifier and the AD7983 analog input circuit must settle for a full-scale step onto the capacitor array at a 16-bit level (0.0015%, 15 ppm). In the data sheet of the amplifier, settling at 0.1% to 0.01% is more commonly specified. This could differ significantly from the settling time at a 16-bit level and should be verified prior to driver selection.
06974-009
Table 8. Recommended Driver Amplifiers
Amplifier ADA4841-x AD8021 AD8022 OP184 AD8655 AD8605, AD8615 Typical Application Very low noise, small and low power Very low noise and high frequency Low noise and high frequency Low power, low noise, and low frequency 5 V single-supply, low noise 5 V single-supply, low power
Rev. 0 | Page 14 of 24
AD7983
VOLTAGE REFERENCE INPUT
The AD7983 voltage reference input, REF, has a dynamic input impedance and should therefore be driven by a low impedance source with efficient decoupling between the REF and GND pins, as explained in the Layout section. When REF is driven by a very low impedance source, for example, a reference buffer using the AD8031 or the AD8605, a ceramic chip capacitor is appropriate for optimum performance. If an unbuffered reference voltage is used, the decoupling value depends on the reference used. For instance, a 22 F (X5R, 1206 size) ceramic chip capacitor is appropriate for optimum performance using a low temperature drift ADR43x reference. If desired, a reference-decoupling capacitor value as small as 2.2 F can be used with a minimal impact on performance, especially DNL. Regardless, there is no need for an additional lower value ceramic decoupling capacitor (for example, 100 nF) between the REF and GND pins.
PSRR (dB)
POWER SUPPLY
The AD7983 uses two power supply pins: a core supply (VDD) and a digital input/output interface supply (VIO). VIO allows direct interface with any logic between 1.8 V and 5.0 V. To reduce the number of supplies needed, VIO and VDD can be tied together. The AD7983 is independent of power supply sequencing between VIO and VDD. Additionally, it is very insensitive to power supply variations over a wide frequency range, as shown in Figure 25.
80
75
70
65
60
1
10
100
1000
FREQUENCY (kHz)
Figure 25. PSRR vs. Frequency
To ensure optimum performance, VDD should be roughly half of REF, the voltage reference input. For example, if REF is 5.0 V, VDD should be set to 2.5 V (5%).
Rev. 0 | Page 15 of 24
06974-010
55
AD7983
DIGITAL INTERFACE
Though the AD7983 has a reduced number of pins, it offers flexibility in its serial interface modes. When in CS mode, the AD7983 is compatible with SPI, QSPI, and digital hosts. This interface can use either a 3-wire or a 4-wire interface. A 3-wire interface using the CNV, SCK, and SDO signals minimizes wiring connections useful, for instance, in isolated applications. A 4-wire interface using the SDI, CNV, SCK, and SDO signals allows CNV, which initiates the conversions, to be independent of the readback timing (SDI). This is useful in low jitter sampling or simultaneous sampling applications. The AD7983, when in chain mode, provides a daisy-chain feature using the SDI input for cascading multiple ADCs on a single data line similar to a shift register. The mode in which the part operates depends on the SDI level when the CNV rising edge occurs. The CS mode is selected if SDI is high, and the chain mode is selected if SDI is low. The SDI hold time is such that when SDI and CNV are connected, the chain mode is always selected. In either mode, the AD7983 offers the flexibility to optionally force a start bit in front of the data bits. This start bit can be used as a busy signal indicator to interrupt the digital host and trigger the data reading. Otherwise, without a busy indicator, the user must time out the maximum conversion time prior to readback. The busy indicator feature is enabled * In CS mode if CNV or SDI is low when the ADC conversion ends (see Figure 29 and Figure 33). * In chain mode if SCK is high during the CNV rising edge (see Figure 37).
Rev. 0 | Page 16 of 24
AD7983
CS MODE, 3-WIRE WITHOUT BUSY INDICATOR
This mode is usually used when a single AD7983 is connected to an SPI-compatible digital host. The connection diagram is shown in Figure 26, and the corresponding timing is given in Figure 27. With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. When a conversion is initiated, it continues until completion irrespective of the state of CNV. This can be useful, for example, to bring CNV low to select other SPI devices, such as analog multiplexers; however, CNV must be returned high before the minimum conversion time elapses and then held high for the maximum conversion time to avoid the generation of the busy signal indicator. When the conversion is complete, the AD7983 enters the acquisition phase and goes into standby mode. When CNV goes low, the MSB is output onto SDO. The remaining data bits are then clocked by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate provided that it has an acceptable hold time. After the 16th SCK falling edge or when CNV goes high, whichever is earlier, SDO returns to high impedance.
CONVERT CNV VIO SDI
DIGITAL HOST
SDO DATA IN
AD7983
SCK
CLK
Figure 26. CS Mode, 3-Wire Without Busy Indicator Connection Diagram (SDI High)
SDI = 1
tCYC tCNVH
CNV
tCONV
ACQUISITION CONVERSION
tACQ
ACQUISITION
tSCK tSCKL
SCK 1 2 3 14 15 16
tHSDO tEN
SDO D15 D14
tSCKH tDSDO
D13 D1 D0
tDIS
06974-013
Figure 27. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing (SDI High)
Rev. 0 | Page 17 of 24
06974-012
AD7983
CS MODE, 3-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7983 is connected to an SPI-compatible digital host that has an interrupt input. The connection diagram is shown in Figure 28, and the corresponding timing is given in Figure 29. With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. SDO is maintained in high impedance until the completion of the conversion irrespective of the state of CNV. Prior to the minimum conversion time, CNV can be used to select other SPI devices, such as analog multiplexers, but CNV must be returned low before the minimum conversion time elapses and then held low for the maximum conversion time to guarantee the generation of the busy signal indicator. When the conversion is complete, SDO goes from high impedance to low. With a pull-up on the SDO line, this transition can be used as an interrupt signal to initiate the data read back controlled by the digital host. The AD7983 then enters the acquisition phase and goes into standby mode. The data bits are then clocked out, MSB first, by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate provided it has an acceptable hold time. After the optional 17th SCK falling edge or when CNV goes high, whichever is earlier, SDO returns to high impedance.
SDI = 1
CNV VIO SDI VIO 47k SDO DATA IN IRQ CLK
06974-014 06974-015
If multiple AD7983s are selected at the same time, the SDO output pin handles this contention without damage or induced latch-up. Meanwhile, it is recommended that this contention be kept as short as possible to limit extra power dissipation.
CONVERT
DIGITAL HOST
AD7983
SCK
Figure 28. CS Mode, 3-Wire with Busy Indicator Connection Diagram (SDI High)
tCYC tCNVH
CNV
tCONV
ACQUISITION CONVERSION
tACQ
ACQUISITION
tSCK tSCKL
SCK 1 2 3 15 16 17
tHSDO tDSDO
SDO D15 D14
tSCKH tDIS
D1 D0
Figure 29. CS Mode, 3-Wire with Busy Indicator Serial Interface Timing (SDI High)
Rev. 0 | Page 18 of 24
AD7983
CS MODE, 4-WIRE WITHOUT BUSY INDICATOR
This mode is usually used when multiple AD7983s are connected to an SPI-compatible digital host. A connection diagram example using two AD7983s is shown in Figure 30, and the corresponding timing is given in Figure 31. With SDI high, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. In this mode, CNV must be held high during the conversion phase and the subsequent data readback (if SDI and CNV are low, SDO is driven low). Prior to the minimum conversion time, SDI can be used to select other SPI devices, such as analog multiplexers, but SDI must be returned high before the minimum conversion time elapses and then held high for the maximum conversion time to avoid the generation of the busy signal indicator. When the conversion is complete, the AD7983 enters the acquisition phase and goes into standby mode. Each ADC result can be read by bringing its SDI input low, which consequently outputs the MSB onto SDO. The remaining data bits are then clocked by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate provided it has an acceptable hold time. After the 16th SCK falling edge or when SDI goes high, whichever is earlier, SDO returns to high impedance and another AD7983 can be read.
CS2 CS1 CONVERT CNV SDI CNV SDO SDI
DIGITAL HOST
SDO
AD7983
SCK
AD7983
SCK
Figure 30. CS Mode, 4-Wire Without Busy Indicator Connection Diagram
tCYC
CNV
tCONV
ACQUISITION CONVERSION
tACQ
ACQUISITION
tSSDICNV
SDI(CS1)
tHSDICNV
SDI(CS2)
tSCK tSCKL
1 2 3 14 15 16 17 18 30 31 32
SCK
tHSDO
SDO
tEN
D15 D14
tDSDO
D13
tSCKH
D1 D0 D15 D14 D1 D0
06974-016
DATA IN CLK
tDIS
06974-017
Figure 31. CS Mode, 4-Wire Without Busy Indicator Serial Interface Timing
Rev. 0 | Page 19 of 24
AD7983
CS MODE, 4-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7983 is connected to an SPI-compatible digital host that has an interrupt input, and when it is desired to keep CNV, which is used to sample the analog input, independent of the signal used to select the data reading. This requirement is particularly important in applications where low jitter on CNV is desired. The connection diagram is shown in Figure 32, and the corresponding timing is given in Figure 33. With SDI high, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. In this mode, CNV must be held high during the conversion phase and the subsequent data readback (if SDI and CNV are low, SDO is driven low). Prior to the minimum conversion time, SDI can be used to select other SPI devices, such as analog multiplexers, but SDI must be returned low before the minimum conversion time elapses and then held low for the maximum conversion time to guarantee the generation of the busy signal indicator. When the conversion is complete, SDO goes from high impedance to low. With a pull-up on the SDO line, this transition can be used as an interrupt signal to initiate the data readback controlled by the digital host. The AD7983 then enters the acquisition phase and goes into standby mode. The data bits are clocked out, MSB first, by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate provided it has an acceptable hold time. After the optional 17th SCK falling edge or SDI going high, whichever is earlier, the SDO returns to high impedance.
CS1 CONVERT CNV SDI VIO 47k SDO DATA IN IRQ CLK
06974-018
06974-019
DIGITAL HOST
AD7983
SCK
Figure 32. CS Mode, 4-Wire with Busy Indicator Connection Diagram
tCYC
CNV
tCONV
ACQUISITION CONVERSION
tACQ
ACQUISITION
tSSDICNV
SDI
tHSDICNV tSCKL
SCK 1 2 3 15
tSCK
16
17
tHSDO tDSDO tEN
SDO D15 D14
tSCKH tDIS
D1 D0
Figure 33. CS Mode, 4-Wire with Busy Indicator Serial Interface Timing
Rev. 0 | Page 20 of 24
AD7983
CHAIN MODE WITHOUT BUSY INDICATOR
This mode can be used to daisy-chain multiple AD7983s on a 3-wire serial interface. This feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. Data readback is analogous to clocking a shift register. A connection diagram example using two AD7983s is shown in Figure 34, and the corresponding timing is given in Figure 35. When SDI and CNV are low, SDO is driven low. With SCK low, a rising edge on CNV initiates a conversion, selects the chain mode, and disables the busy indicator. In this mode, CNV is held high during the conversion phase and the subsequent data readback. When the conversion is complete, the MSB is output onto SDO and the AD7983 enters the acquisition phase and goes into standby mode. The remaining data bits stored in the internal shift register are clocked by subsequent SCK falling edges. For each ADC, SDI feeds the input of the internal shift register and is clocked by the SCK falling edge. Each ADC in the chain outputs its data MSB first, and 16 x N clocks are required to readback the N ADCs. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate and, consequently, more AD7983s in the chain, provided the digital host has an acceptable hold time. The maximum conversion rate can be reduced due to the total readback time.
CONVERT CNV SDI CNV SDO SDI
DIGITAL HOST
SDO DATA IN
AD7983
A SCK
AD7983
B SCK
Figure 34. Chain Mode Without Busy Indicator Connection Diagram
SDIA = 0 CNV
tCYC
tCONV
ACQUISITION CONVERSION
tACQ
ACQUISITION
tSCK tSSCKCNV
SCK 1 2 3
tSCKL
14 15 16 17 18 30 31 32
tHSCKCNV tEN
SDOA = SDIB DA15
tSSDISCK tHSDISCK
DA14 DA13 DA1
tSCKH
DA0
tHSDO tDSDO
SDOB DB15 DB14 DB13 DB1 DB0 DA15 DA14 DA1 DA0
06974-021
Figure 35. Chain Mode Without Busy Indicator Serial Interface Timing
Rev. 0 | Page 21 of 24
06974-020
CLK
AD7983
CHAIN MODE WITH BUSY INDICATOR
This mode can also be used to daisy-chain multiple AD7983s on a 3-wire serial interface while providing a busy indicator. This feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. Data readback is analogous to clocking a shift register. A connection diagram example using three AD7983s is shown in Figure 36, and the corresponding timing is given in Figure 37. When SDI and CNV are low, SDO is driven low. With SCK high, a rising edge on CNV initiates a conversion, selects the chain mode, and enables the busy indicator feature. In this mode, CNV is held high during the conversion phase and the subsequent data readback. When all ADCs in the chain have completed their conversions, the SDO pin of the ADC closest to the digital host (see the AD7983 ADC labeled C in Figure 36) is driven high. This transition on SDO can be used as a busy indicator to trigger the data readback controlled by the digital host. The AD7983 then enters the acquisition phase and goes into standby mode. The data bits stored in the internal shift register are clocked out, MSB first, by subsequent SCK falling edges. For each ADC, SDI feeds the input of the internal shift register and is clocked by the SCK falling edge. Each ADC in the chain outputs its data MSB first, and 16 x N + 1 clocks are required to readback the N ADCs. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate and, consequently, more AD7983s in the chain, provided the digital host has an acceptable hold time.
CONVERT CNV SDI CNV SDO SDI CNV SDO SDI
DIGITAL HOST
SDO DATA IN IRQ CLK
06974-022
AD7983
A SCK
AD7983
B SCK
AD7983
C SCK
Figure 36. Chain Mode with Busy Indicator Connection Diagram
tCYC
CNV = SDIA
tCONV
CONVERSION
tACQ
ACQUISITION
ACQUISITION
tSCK tSSCKCNV
SCK 1 2 3
tSCKH
4 15 16 17 18 19 31 32 33 34 35 47 48 49
tHSCKCNV tEN
SDOA = SDIB
tSSDISCK tHSDISCK
DA15 DA14 DA13 DA1
tSCKL
DA0
tDSDOSDI
tHSDO tDSDO
SDOB = SDIC
tDSDOSDI
DB1 DB0 DA15 DA14 DA1 DA0
tDSDOSDI tDSDOSDI
DB15
DB14
DB13
tDSDODSI
DC15 DC14 DC13 DC1 DC0 DB15 DB14 DB1 DB0 DA15 DA14 DA1 DA0
06974-023
SDOC
Figure 37. Chain Mode with Busy Indicator Serial Interface Timing
Rev. 0 | Page 22 of 24
AD7983 APPLICATION HINTS
LAYOUT
The printed circuit board (PCB) that houses the AD7983 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. The pinout of the AD7983, with all its analog signals on the left side and all its digital signals on the right side, eases this task. Avoid running digital lines under the device because these couple noise onto the die, unless a ground plane under the AD7983 is used as a shield. Fast switching signals, such as CNV or clocks, should never run near analog signal paths. Crossover of digital and analog signals should be avoided. At least one ground plane should be used. It can be common or split between the digital and analog section. In the latter case, the planes should be joined underneath the AD7983. The AD7983 voltage reference input REF has a dynamic input impedance and should be decoupled with minimal parasitic inductances. This is done by placing the reference decoupling ceramic capacitor close to, ideally right up against, the REF and GND pins and connecting them with wide, low impedance traces. Finally, the AD7983 power supplies, VDD and VIO, should be decoupled with ceramic capacitors, typically 100 nF, placed close to the AD7983 and connected using short and wide traces to provide low impedance paths and to reduce the effect of glitches on the power supply lines.
06974-025 06974-024
AD7983
Figure 38. Example Layout of the AD7983 (Top Layer)
An example of a layout following these rules is shown in Figure 38 and Figure 39.
EVALUATING THE PERFORMANCE OF THE AD7983
Other recommended layouts for the AD7983 are outlined in the documentation of the evaluation board for the AD7983 (EVAL-AD7983CBZ). The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the EVAL-CONTROL BRD.
Figure 39. Example Layout of the AD7983 (Bottom Layer)
Rev. 0 | Page 23 of 24
AD7983 OUTLINE DIMENSIONS
3.10 3.00 2.90 3.10 3.00 2.90 PIN 1 0.50 BSC 0.95 0.85 0.75 0.15 0.05 0.33 0.17 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA 1.10 MAX 8 0 0.80 0.60 0.40
10 6
1
5
5.15 4.90 4.65
SEATING PLANE
0.23 0.08
Figure 40.10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters
3.00 BSC SQ 0.30 0.23 0.18
6 10 *EXPOSED PAD (BOTTOM VIEW)
0.50 BSC
PIN 1 INDEX AREA 0.50 0.40 0.30
TOP VIEW
1.74 1.64 1.49
5
1
0.80 0.75 0.70 SEATING PLANE
0.80 MAX 0.55 NOM
2.48 2.38 2.23 0.05 MAX 0.02 NOM
PIN 1 INDICATOR (R 0.19)
Figure 41. 10-Lead Lead Frame Chip Scale Package [QFN (LFCSP_WD)] 3 mm x 3 mm Body, Very Very Thin, Dual Lead (CP-10-9) Dimensions shown in millimeters QFN package in development. Contact sales for samples and availability.
ORDERING GUIDE
Model AD7983BRMZ 1 AD7983BRMZRL71 EVAL-AD7983CBZ1, 2 EVAL-CONTROL BRD 3
1 2
Temperature Range -40C to +85C -40C to +85C
Ordering Quantity Tube, 50 Reel, 1000
Package Description 10-Lead MSOP 10-Lead MSOP Evaluation Board Controller Board
Package Option RM-10 RM-10
101207-B
0.20 REF
*PADDLE CONNECTED TO GND. THIS CONNECTION IS NOT REQUIRED TO MEET THE ELECTRICAL PERFORMANCES.
Branding C5Y C5Y
Z = RoHS Compliant Part. This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD3 for evaluation/demonstration purposes. 3 This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designator.
(c)2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06974-0-11/07(0)
Rev. 0 | Page 24 of 24

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